Fabrication of semiconductor devices

ABSTRACT

The disclosure herein pertains to methods for fabricating planar, discrete or monolithic arrays of semiconductor devices, particularly light-emitting diodes and arrays thereof. The disclosure more particularly concerns diffusion processes to form controlled regions of P-type conductivity in N-type conductivity semiconductors.

United States Patent 91 Schmidt [45] Apr. 24, 1973 FABRICATION OFSEMICONDUCTOR OTHER PUBLICATIONS DEVICES Electronics June 12, 1967,pages 82-90, Gallium lflventori J Schmidt, s, Mo. Arsenide FETsOutperform Conventional Silicon [73] Assignee: Monsanto Company, St.Louis, Mo. MOS D evlces",

[ Filedl P 1971 Primary Examiner-Charles W. Lanham Appl. No.: 134,240

Assistant ExaminerW. Tupman Att0rney-William I. Andress, Neal E. Willisand J. D. Upham 5 7 ABSTRACT The disclosure herein pertains to methodsfor fabricating planar, discrete or monolithic arrays of semiconductordevices, particularly light-emitting diodes and arrays thereof. Thedisclosure more particularly concerns diffusion processes to formcontrolled regions of P-type conductivity in N-type conductivitysemiconductors.

6 Claims, 15 Drawing Figures Patented April 24, 1973 I 3,728,784

a Sheets-Sheet 1 FlGi INVENTOR JOHN G. SCHMIDT ATTORNEY 5 Sheets-Sheet 3l NVENTOR JOHN G. SCHMIDT BY (fi /14m M ATTORNEY FABRICATION OFSEMICONDUCTOR DEVICES BACKGROUND OF THE INVENTION This inventionpertains to the field of semiconductor devices, particularlylight-emitting devices, and fabrication methods therefor.

As pertains to a primary aspect of this invention, the prior artdescribes numerous methods for fabricating semiconductor devices whereinconventional photolithographic techniques are used in conjunction withvarious masking, impurity diffusion and etching system to provide one ormore regions of one conductivity type in semiconductor bodies of anotherconductivity type. By variations of these techniques simple or complexsemiconductor components may be fabricated to produce a variety ofelectronic devices, including light-emitting devices.

Among the various diffusion systems described in the prior art are vaporphase, solid phase and liquid phase diffusions of the conductivity-typedetermining impurity into the masked or unmasked semiconductor substratebody to provide active regions therein. Some of the diffusions describedin the prior art must be conducted in evacuated and sealed ampoules(closed tube diffusion), while others may be performed as an opentubediffusion.

With respect to various diffusion/masking systems, it is known to use alayer of SiO or impurity-doped SiO through which, or through windows ofwhich, certain impurities may be diffused into the semiconductor waferor to use an impurity-doped Si or SiO layer from which the impurity isdiffused into the semiconductor substrate. See, e.g., US. Pat. Nos.3,255,056, 3,352,725, 3,450,581, 3,502,517, 3,502,518 and 3,530,015. Itis also known to use diffusion masks of silicon nitride which may befurther coated with silicon (US. Pat. No. 3,537,921) or metals (US. Pat,No. 3,519,504) which are deposited in direct contact with a surface Fthe semiconductor body. Another masking/diffusion system involves maskshaving separate, distinct portions consisting, respectively, of variousoxides, e.g., SiO and laminated Si N /SiO SiO /Si N /SiO this lattertype of combination mask has been described (US. Pat. No. 3,484,313) inconnection with a selective diffusion process for diffusing a pluralityof different types of impurities into different regions of asemiconductor body, each portion of the mask being effective to block orpartially block specified impurities.

Problems commonly encountered in most prior art diffusion systemsinclude poor control and reproducibility of the impurity surfaceconcentration, diffusion profile, junction depth and planarity of theP-N junction. Still other problems relate to masking systems used; forexample, lack of adhesion of the mask to the semiconductor surface;permeability of the mask to the in-diffusing impurity and/orout-diffusion of volatile constituents or desired impurities inintermetallic or elemental semiconductors, thus requiring very thick orheavily-doped masking layers; reactivity of the masking material withthe impurity and/or semiconductor body and necessity to use aclosed-tube diffusion with some masking systems.

Therefore, it is an object of the present invention to provide a uniquediffusant-masking system for fabricating semiconductor devices.

More particularly, it is an object of this invention to provide asolid-solid, open-tube diffusion process which overcomes theabove-mentioned problems.

Still more particularly, it is an object of the present invention toprovide a diffusion system which is controllable, simple and economical.

These and other objects will become apparent from the detaileddescription given below.

SUMMARY OF THE INVENTION This invention relates to a unique impuritydiffusantmasking system to fabricate semiconductor devices; in preferredembodiments, planar, discrete or monolithic arrays of light-emittingdiodes (LEDs) are provided.

The semiconductor device fabrication process herein comprises the use ofan impurity diffusion system consisting of an SiO /ZnO/densified SiOsandwich-structure diffusant source in conjunction with an SiO /Si N/SiO sandwich-structure diffusion mask; both the diffusant source anddiffusion mask being in intimate contact with the semiconductor body ofN-type conductivity, to provide a means of diffusing zinc into selectedareas (of any configuration) thereof. Upon heating the structure, zincis diffused from the diffusant source to form a region of P-typeconductivity in the N-type semiconductor substrate body.

An additional feature of this invention involves the formation of metalcontact P regions within the P region resulting from the abovediffusion. The P region may be formed in any known manner, e.g., byclosedtube diffusion using elemental zinc, zinc arsenide or azinc/gallium alloy, or by open-tube diffusion using the above SiO/ZnO/densified SiO diffusant or a zincdoped silica diffusion layer.Thereafter, ohmic contact is made to the P surface in the P region ofthe semiconductor by metallization through windows in a photoresistmask, and ohmic contact is made to the N surface, preferably by means of4 alloying successive layers of tin and gold with the semiconductormaterial, followed by deposition of successive layers of nickel andgold. A lead wire is bonded to the P contact and the device attached bythe N contact to a base or header, then encapsulated.

BRlEF DESCRIPTION OF THE DRAWINGS FlGS. 1-12 are cross-sectionalschematic views of a semiconductor wafer during successive steps, priorto applying the P contact metallization pattern in the fabrication of anLED.

FIG. 13 is a cross-sectional schematic view taken along horizontal line8-8 of a completely fabricated LED (shown in plan view in FIG. 15).

FIG. 14 is a cross-sectional schematic view taken along line A-A' of theLED shown in FIG. 15.

FIG. 15 is a top plan view of one embodiment of an LED fabricatedaccording to this invention.

DESCRlPTlON OF PREFERRED EMBODIMENTS The present invention in itspreferred embodiments relates to a method for fabricating planarlight-emitting semiconductor devices, either as discrete LEDs or as anarray of LEDs on a monolithic semiconductor substrate. Preferredsemiconductor materials include gallium arsenide, gallium phosphide andgallium arsenide phosphide.

' EXAMPLE In a preferred embodiment of this invention, LEDs are preparedwith gallium arsenide (GaAs) as the semiconductor component of thedevice.

Referring to the drawings, which show successive stages in thefabrication process, FIG. 1 represents a cleaned and polished GaAs waferl in cross-section schematic view. The GaAs is of N-type conductivitydoped with silicon to a carrier concentration suitably within the rangeof about 15 l0 atoms/cc. In FIG. 2, A layer 2 of Si about l,500 A thickis deposited on the back (bottom) surface and a layer 3 of SiO;, about200 A thick is deposited on the front (top) surface of the GaAssubstrate wafer 1; these SiO layers may be prepared and deposited byvarious means known to the art and in this example, by reacting silane(SiH with oxygen carried by nitrogen at temperature of from 300400 C todeposit SiO on the GaAs wafer. A

layer 4 of silicon nitride, Si N is then formed, e.g., by reactingsilane with ammonia in forming gas (95 percent N 5 percent H at 800900 Cto deposit the Si N layer 4 atop SiO layer 3 as shown in FIG. 3. At thetemperatures required for the formation and deposition of Si N thevolatile component of the semiconductor, arsenic in this example, tendsto outdiffuse from the GaAs; hence, SiO layer 2 is used to prevent suchout-diffusion. The Si N, layer in this example is about 350 A thick, butsuitably may be thicker. A layer 5 of SiO from 1,500 A to 2,000 A thickis then deposited, in the manner described above, atop the Si N layer 4as shown in FIG. 4. SiO layer 5 serves as a mask to define the patternto be etched in the Si N layer.

Using conventional photolithographic techniques, a window 6, shown inFIG. 5, is then etched through the SiO layer 5 with a mixture of NHF'I-IF'H O. The photoresist layer (not shown) is then removed from SiOlayer 5 and a window, within the same region defined by the symbol 6, isetched through the Si N layer 4 with hot 170 C) concentrated phosphoricacid, which has negligible effect on the SiO as shown in FIG. 5. Againusing the mixed NI-I F-HF'H O etchant, a window is etched within reGion6 (FIG. 5) through SiO layer 3 to expose a surface (diffusion) region 7of the GaAs substrate 1 and simultaneously etch away the remainingportion of SiO layer 5; SiO layer 2 is also removed by the etchingoperation, leaving the structure shown in FIG. 6.

After opening the window through SiO and Si N layers as described, thewafer is then rinsed with deionized water (DI), dried, cleaned with NI-IOH, rinsed again with DI, then with isopropyl alcohol (IPA) and againdried. A fresh layer 9 of SiO; is then deposited over the back surfaceof the GaAs wafer (to prevent out-diffusion of arsenIc during subsequenttreatment) and a fresh layer'8 of SiO, is also deposited on the frontsurface of the wafer covering the Si N layer 4 and surface region 7 ofthe wafer as shown in FIG. 7; these SiO, layers 8 and 9 are both about1,200 A thick. The

wafer is now heat treated at about 875 C or, generally,

within the range of from 800950 C, in forming gas for about 1 hour. Thisisa highly important step, involving annealing of the SiO /GaAsinterface as well as forming a densitied modulating layer 8 for thesubsequent diffusion of zinc therethrough, thus providing furthercontrol of the zinc diffusion into the GaAs wafer. This step intheprocess is not necessary when the substrate material is GaP.

Following the heat treatment, a layer 10 of zinc oxide (ZnO) about 300 Athick is deposited on layer 8 as shown in FIG. 8. The ZnO layer' isformed and deposited by reacting diethyl zinc, carried in nitrogen,

with oxygen at about 400 C or, generally, within the range of from300500 C. A final layer 11 of SiO about 500 A thick is then depositedover the ZnO layer as shown in FIG. 9. The Si0 layer tends toretardoutdiffusion of zinc from the ZnO layer. The wafer thus preparedis then transferred to an open tube diffusion furnace and heated to 875C in forming gas for 7 hours. Zinc is diffused from the ZnO layerthrough the modulating SiO layer 8 into the substrate wafer to form agraded P region 11 (FIG. 9) approximately 6 microns below the surfacewhich has a surface zinc concentration of about 3X10 atoms/cc.

It will be apparent that the diffusion times and temperature may bevaried with a variation of the thicknesses of the ZnO and modulatingSiO; layers, zinc concentration and junction depth of the P region andsemiconductor substrate material. For example, when the semiconductormaterial to be diffused is GaP or GaAsP, the diffusion time is 30minutes at the same temperature used for GaAs diffusions.

After the diffusion operation the cooled wafer is then treated inaqueous HP or a 1:8 parts by volume aqueous mixture of I-IF:NH F for atime, less than a minute, sufficient to etch away the SiO layer 9 andthe SiO /Z- nO/SiO diffusant layers (8, 10 and 11) shown in FIG. 9 andleave the Si N /SiO masked structure shown in FIG. 10. This structure isthen cleaned with sequential treatments with hot HCl, DI,,isopropylalcohol (IPA), dried, soaked in NI-I OI-I for a few minutes, and againtreated with DI, IPA, then dried. The cleaned wafer is then transferredto an SiO reactor where a fresh layer 12 of SiO about 3,000 A thick isdeposited on the top surface of the wafer as shown in FIG. 11. Usingthis basic structure any desired metallization pattern may be formed onthe device by use of conventional photolithographic techniques.

As illustrative LED devices fabricated according to this invention, thefollowing description will refer to fabrication of the device shown intop plan view in FIG. 15. Referring to FIG. 12, (which, together withFIGS. 13 and 14, has been enlarged for clarity), windows (holes orapertures) 14 and 15 are opened through SiO layer 12 by photomasking andetching to expose surface areas of the GaAs substrate to which metalcontacts are to be made. Prior to metallization, it has been found thatsuperior contact may be made to GaAs wafers by forming P regions in theP layer defined by the area under windows 14 and 15. This isaccomplished by flash diffusing additional zinc into the P layer exposedby the windows by any suitable means. For example, by use of the'aboveSiO /ZnO/SiO, diffusant, or a zinc-doped silica film may be spun ontothe wafer and heated in an open tube diffusion furnace at 875 for 5-8minutes in forming gas. Another method utilizes a closed-tube vapordiffusion of zinc from various sources, e.g., from zinc arsenide, thediffusion being conducted at 800 for 5-8 minutes. The flash diffusionoperation and P regions have not as yet been found particularly helpfulin making superior metal contact to GaP or GaAsP as with GaAs.

After the P regions are formed, aluminum is then vacuum evaporated to athickness of l,000-l,500 A over the surface of the wafer making contactwith the P regions of the GaAs wafer. Using photomasking and etching,the aluminum metallization pattern 18 is defined on the LED device asshown in FIG. FIG. 13 is a cross-sectional view of the device takenalong the horizontal line BB and FIG. 14 is a cross-sectional view takenalong diagonal line AA' in FIG. 15.

After the wafer has been cleaned, ohmic contact is made to the back (Nsurface) by any suitable means. A preferred ohmic contact method isdisclosed and claimed in copending application, U.S. Ser. No. 21,637,filed Mar. 23, 1970 and assigned to the assignee of thls application.That method involves vacuum evaporating first a layer of tin, then alayer of gold onto the N-surface, heating the wafer to alloy the tin andgold with a surface region of GaAs to form an N region 19 therein asshown in FIGS. 13 and 14; a

layer of nickel 20 is then electroless plated onto the N region followedby electroless plating a layer of gold 21 to the nickel. Alternatively,the tin, gold, nickel and gold layers may be first deposited then allfour alloyed together with a surface region of GaAs to form the N region19 therein. Thereafter, the device is attached, N side down, to a postor header (not shown), a wire lead 22 bonded to the aluminum in the area23, e.g., as shown in FIGS. 14 and 15 and, finally, encapsulated in asuitable lens (not shown) for LEDs, e.g., clear epoxy.

The preferred embodiment of the invention described herein is by way ofillustration only, and not limitation. Other semiconductor materials inthe III-V family of intermetallic compounds and mixtures or alloysthereof may be diffused according to the process of this invention ashereinabove described with reference to GaAs, GaP and GaAs P where Xrepresents a numerical value from zero to one (I) inclusive. The use ofimpurity oxides other than ZnO, e.g., CdO, in the same structural andfunctional relationship to the diffusion mask and semiconductor iswithin the purview ofthis invention, as well as other impurity blockingsubstitutes for the Si N layer exemplified. These and othermodifications of the invention will occur to those skilled in the artwithout departing from the spirit and scope thereof.

I claim:

1. Process for fabricating semiconductor devices which comprises:

a. providing a semiconductor substrate;

b. applying to the front surface of said substrate a laminated impuritydiffusion masking system consisting of a layer of Si N sandwichedbetween layers of SiO- c. etching diffusion windows through saiddiffusion masking system to expose diffusion surfaces of said substrate;

d. depositing a layer of SiO- over the back surface of said substrateand another layer of Si0 over the front of said substrate;

e. heat treating the structure of step (d);

depositing a layer of impurity oxide onto said layer of SiO deposited onthe front surface of said substrate in step (d);

. depositing a layer of SiO onto said layer ofimpurity oxide;

h. heating the structure of step (g) to diffuse impurities from saidimpurity oxide into said semiconductor;

i. etching from the structure of step (h) the oxide layers deposited insteps (d), (f) and (g);

j. depositing a layer of SiO over the front surface of said substrate;

k. etching windows through the SiO layer deposited in step (j) to exposeselected areas of said substrate previously diffused with impurities bystep l. diffuse an additional amount of said impurities into saidselected areas of said substrate;

m. applying ohmic contact material in the desired pattern to the frontsurface of said substrate and in contact therewith at said selectedareas;

n. applying ohmic contact to the back surface of said substrate;

0. affixing electrical leads to an external circuit and p. encapsulatingthe device.

2. Process according to claim 1 wherein said impurity oxide is ZnO.

3. Process according to claim 2 wherein said semiconductor substrate isof N-type conductivity and is selected from the group consisting ofIII-V compounds and mixtures thereof.

4. Process according to claim 3 wherein said semiconductor substrate isGaAs P where X is a number fromzero to one inclusive.

5. Process according to claim 4 wherein X equals one and saidsemiconductor substrate is GaAs.

6. Process according to claim 5 wherein the semiconductor device is alight-emitting device and is encapsulated in transparent material.

1. Process for fabricating semiconductor devices which comprises: a.providing a semiconductor substrate; b. applying to the front surface ofsaid substrate a laminated impurity diffusion masking system consistingof a layer of Si3N4 sandwiched between layers of SiO2; c. etchingdiffusion windows through said diffusion masking system to exposediffusion surfaces of said substrate; d. depositing a layer of SiO2 overthe back surface of said substrate and another layer of SiO2 over thefront of said substrate; e. heat treating the structure of step (d); f.depositing a layer of impurity oxide onto said layer of SiO2 depositedon the front surface of said substrate in step (d); g. depositing alayer of SiO2 onto said layer of impurity oxide; h. heating thestructure of step (g) to diffuse impurities from said impurity oxideinto said semiconductor; i. etching from the structure of step (h) theoxide layers deposited in steps (d), (f) and (g); j. depositing a layerof SiO2 over the front surface of said substrate; k. etching windowsthrough the SiO2 layer deposited in step (j) to expose selected areas ofsaid substrate previously diffused with impurities by step (h); l.diffuse an additional amount of said impurities into said selected areasof said substrate; m. applying ohmic contact material in the desiredpattern to the front surface of said substrate and in contact therewithat said selected areas; n. applying ohmic contact to the back surface ofsaid substrate; o. affixing electrical leads to an external circuit andp. encapsulating the device.
 2. Process according to claim 1 whereinsaid impurity oxide is ZnO.
 3. Process according to claim 2 wherein sAidsemiconductor substrate is of N-type conductivity and is selected fromthe group consisting of III-V compounds and mixtures thereof.
 4. Processaccording to claim 3 wherein said semiconductor substrate is GaAs1 XPX,where X is a number from zero to one inclusive.
 5. Process according toclaim 4 wherein X equals one and said semiconductor substrate is GaAs.6. Process according to claim 5 wherein the semiconductor device is alight-emitting device and is encapsulated in transparent material.